The present invention relates to an electronic sample and hold circuit and more particularly to a sample and hold circuit suitable to be provided in monolithic integrated circuit form.
Many applications can be envisioned for sample and hold circuits. For example, one such application is as a peripheral unit for interfacing between a computer and a time varying analog signal. Another application may be as a means for sampling a time varying input signal to permit analog to digital conversion of the input signal at predetermined times. One further application may be as a means for sampling a signal which is to be coded for transmission and reception in a communication system.
Most contemporary sample and hold circuits are comprised of discrete circuitry. Thus the size of such circuits is relatively large with respect to monolithic integrated circuits which are produced and fabricated today.
Moreover, contemporary sample and hold circuits include passive components (resistors, capacitors), active switches and operational amplifiers which respond to externally generated sampling pulses to sample the time varying input signal for deriving an output signal the level of which corresponds to the magnitude of the input signal at the termination of the sampling pulse. However, a major problem associated with these types of sample and hold circuits is that they suffer from error signals which limit the accuracy of the output level produced. One such source of error arises from the DC offset voltage of the operational amplifiers which are most commonly used. Offset voltage is defined as the difference in dc input voltages required at the input terminals of the operational amplifier to produce a zero output voltage therefrom. In order to compensate for offset voltages, prior art sample and hold circuits require an offset nulling potentiometer as part of the circuit. However, even though the offset voltage may be nulled at one particular input signal level, operation at a different input signal level may introduce an error in the output signal due to imperfect common mode rejection ratio in the operational amplifier. In addition, the thermal dependence of the offset voltage makes it quite difficult to compensate therefor over temperature variations. As the environmental operating temperature varies, manual adjustment of the nulling adjustment must be made to maintain circuit accuracy. As an example, commercially available sample and hold circuits typically have temperature coefficients in the range of 10 ppm/.degree. C to 100 ppm/.degree. C. Thus, as temperature varies, to maintain accuracies, the prior art circuit must be nulled continuously.
Further, the precision with which sampling is effected in the prior art circuits is also a function of the common mode rejection ratio (CMRR) factor of the operational amplifiers. The nulling adjustment common to most sample and hold circuits is used for adjustment of offset voltages, a direct current (dc) parameter. However, as the input signal is normally a time varying function, as the magnitude of the input voltage varies so does the offset voltage of the operational amplifier. Thus, even though accuracy adjustments can be made to the prior art circuits for a desired input signal level, error is still introduced during sampling because of CMRR.
One further problem associated with prior art sample and hold circuits is that the sampling pulse rate is limited by the slew rate of the operational amplifiers comprising the circuit. Thus the prior art circuits are slew rate limited on acquisition time.
Thus, a need exists for an improved sample and hold circuit having self compensation for output offset voltage and common mode rejection in order that a manual accuracy adjustment is not required. By elimination of these errors, a sample and hold circuit having essentially zero temperature coefficient may be produced. A further need exists for a sample and hold circuit which is not slew rate limited.